1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device.
2. Discussion of the Related Art
Until now, the cathode-ray tube (CRT) has been developed and mainly used for display systems. However, flat panel displays are beginning to make an appearance because of their small depth dimensions, desirably low weight, and low voltage power supply requirements. Presently, thin film transistor-liquid crystal displays (TFT-LCDs) with high resolution and small depth dimension are being developed.
In general, liquid crystal display (LCD) devices make use of optical anisotropy and polarization properties of liquid crystal molecules to control arrangement orientation. The arrangement direction of the liquid crystal molecules can be controlled by an applied electric field. Accordingly, when an electric field is applied to liquid crystal molecules, the arrangement of the liquid crystal molecules changes. Since refraction of incident light is determined by the arrangement of the liquid crystal molecules, display of image data can be controlled by changing the electric field applied to the liquid crystal molecules.
Of the different types of known LCDs, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, are the subject of significant research and development because of their high resolution and superiority in displaying moving images.
LCD devices have wide application in office automation (OA) equipment and video units because of their light, thin, low power consumption characteristics. The typical liquid crystal display (LCD) panel has an upper substrate, a lower substrate and a liquid crystal layer interposed therebetween. The upper substrate, commonly referred to as a color filter substrate, usually includes a common electrode and color filters. The lower substrate, commonly referred to as an array substrate, includes switching elements, such as thin film transistors (TFTs), and pixel electrodes.
FIG. 1 is a schematic cross-sectional view illustrating a pixel of a conventional LCD panel having an inverted staggered type TFT as a switching device. As shown, the LCD panel 20 has lower and upper substrates 2 and 4 and a liquid crystal (LC) layer 10 interposed therebetween. The lower substrate 2 has a thin film transistor (TFT) “S” as a switching element that switches a voltage that changes the orientation of the LC molecules. The lower substrate 2 also includes a pixel electrode 4 on a transparent substrate 1 which is used to apply an electric field across the LC layer 10 in response to signals applied to the TFT “S”. The upper substrate 4 has a color filter 8 for producing a color, and a common electrode 12 on the transparent substrate 1 and on the color filter 8. The common electrode 12 serves as an electrode that produces the electric field across the LC layer (with the assistance of the pixel electrode 14). The pixel electrode 14 is arranged over a pixel portion “P,” i.e., a display area. Further, to prevent leakage of the LC layer 10, substrates 2 and 4 are sealed by a sealant 6.
Although FIG. 1 only shows one inverted staggered type TFT “S”, the lower substrate 2 usually includes a plurality of TFTs as well as a plurality of pixel electrodes each contacting each TFT. In the above-mentioned panel 20, the lower substrate 2 and the upper substrate 4 are respectively formed through different processes and then attached each other.
FIG. 2 is a schematic plan view illustrating a portion of an array substrate having inverted staggered type TFTs of FIG. 1. As shown in FIG. 2, a gate shorting bar 36 and a plurality of gate pads 35 are formed in a peripheral portion of the transparent substrate 1. A plurality of gate lines 30 are transversely connected to the plurality of respective gate pads 35. A data shorting bar 46 is disposed in an edge portion of the transparent substrate 1 adjacent to the peripheral portion where the gate shorting bar 36 is disposed. A plurality of data pads 45 are electrically connected to the data shorting bar 46, and a plurality of data lines 40 are electrically connected to respective data pads 45. Each data line 40 is substantially perpendicular to the plurality of gate lines 30, and the gate lines 30 and the data lines 40 define pixel regions where each pixel electrode 14 is disposed respectively.
The plurality of data pads 45 and the data shorting bar 46 can be formed together with the plurality of data lines 40 at the same time. However, in order to reduce the fabricating process steps, the plurality of data pads 45 and the data shorting bar 46 are usually formed with the gate lines 30, and each data pad 45 is electrically connected to each data line 40 with connector through a data pad contact hole (not shown).
For more detailed explanation, the interconnection of the above-mentioned lines, pads and shorting bars is depicted in FIG. 3. As shown in FIG. 3, the plurality of gate lines can be classified into odd numbered lines 30a and even numbered lines 30b, and the plurality of gate pads 35 can also be classified into odd numbered gate pads 35a and even numbered gate pads 35b. Each odd numbered gate line 30a connects with a respective odd numbered gate pad 35a, which is electrically connected with a first shorting bar 36a, while each even numbered gate line 30b connects with a respective even numbered gate pad 35b, which is electrically connected to a second shorting bar 36b. This grouping and structure can be adapted for the data line, pad and shorting bar, thereby classifying the data lines into odd numbered data line 40a and even numbered data line 40b in FIG. 3.
As mentioned before, the odd 40a and even 40b numbered data lines are perpendicular to the plurality of gate lines 30a and 30b, and the gate lines and the data lines define a plurality of pixel regions. Thus, each pixel electrode 14 is disposed in each respective pixel region. A thin film transistor (TFT) “S” is also disposed at a corner of each pixel region. Each TFT “S” is electrically connected to the gate and data lines, and each pixel electrode 14 electrically connects with each TFT “S.”
Still referring to FIG. 3, the first and second gate shorting bars 36a and 36b are parallel with each other and perpendicular to the gate lines 30a and 30b. Additionally, these shorting bars 36a and 36b are formed together when the gate lines 30a and 30b are formed, and the second gate shorting bar 36b is disposed in a further outer portion of the transparent substrate 1 than the first gate shorting bar 36a. The first gate shorting bar 36a is electrically connected to the odd numbered gate lines 30a directly and to the even numbered gate lines 30b through a plurality of first connecting lines 31. Namely, each first connecting line 31 protrudes from the first gate shorting bar 36a and has an L-shape to connect the first gate shorting bar 36a to the corresponding even numbered gate pad 35b. However, the odd numbered gate pads 35a are directly connected to the first gate shorting bar 36a. According to this structure, the first shorting bar 36a prevents discharge of static electricity from occurring in the odd and even numbered gate lines 30a and 30b during fabrication processes. In other words, because transparent glass substrates are conventionally used for substrates of LCD devices, any static electricity generated during manufacturing processes will flow into array pattern portions of the array substrate. Accordingly, the TFTs, the gate lines and the data lines are all susceptible to significant damage as a result of any discharge of the static electricity. To prevent any damage due to any static electrical discharge, shorting bars are connected with gate lines.
In FIG. 3, the first connecting line 31 is disconnected for short/open-circuit test of the gate lines in a later manufacturing step. Namely, the TFTs “S” are tested for proper operation using the first and second gate shorting bars 36a and 36b. The first gate shorting bar 36a is connected to only the odd numbered gate lines 30a by way of cutting the first connecting lines 31. Additionally, only the second gate shorting bar 36b is connected to the even numbered gate lines using a second connecting line 34. This second connecting line 34 electrically connects the second gate shorting bar 36b to the even numbered gate pad 35b through contact holes that are respectively formed on the second gate shorting bar 36a and on a portion of the disconnected first connecting line 31. The second connecting line 34 can be formed with the data lines 40a and 40b or with the pixel electrodes 14. Although FIG. 3 depicts the gate lines, the gate pads and the gate shorting bars, the above-mentioned connections and configuration can be adapted to the data lines, pads and shorting bars.
After the short/open-circuit test, the array substrate 2 is attached to the color filter substrate. Thereafter, the peripheral portions of the array substrate 2 are cut along line A—A or B—B in order to detach unnecessary areas from the array substrate 2.
FIGS. 4A to 4D are cross-sectional views taken along line IV—IV of FIG. 3 and show conventional fabricating processes of an array substrate having inverted staggered type TFTs “S” of FIG. 3.
Referring to FIG. 4A, a first metal layer is formed on the transparent substrate 1, and then a positive photo resist is deposited on the first metal layer. The deposited photo resist is exposed to light using a first mask and then developed. Thereafter, the first metal is patterned using an etchant, and then the residual photo resist on the patterned metal layer is removed, thereby forming a gate electrode 32 and the first connecting line 31. At this time, the first and second gate shorting bars 36a and 36b (in FIG. 3) are also formed. Further, the odd and even numbered gate lines 30a and 30b and pads 35a and 35b (in FIG. 3) are formed together with the gate electrode 32. Additionally, the data shorting bars and data pads (not shown) can be formed at the time when the gate electrode 32 is formed.
Now, referring to FIG. 4B, a gate insulation layer 34, which is silicon nitride (SiNX) or silicon oxide (SiOX), is formed on an entire surface of the transparent substrate 1 and covers the patterned first metal layer. Then, an active layer 37 (i.e., a pure amorphous silicon (a-Si:H)) and an ohmic contact layer 38 (i.e., a doped amorphous silicon (n+ a-Si:H)) are formed in series upon the gate insulation layer 34, especially over the gate electrode 32.
In FIG. 4C, a second metal layer, which is molybdenum (Mo), is formed upon an entire surface of the gate insulation layer 34, thereby covering the active layer 37 and ohmic contact layer 38. Thereafter, a positive photo resist is formed on the Mo metal layer, exposed using a mask, and then developed in a desired pattern. The Mo metal layer is etched using an etchant, thereby forming a source electrode 42 and a drain electrode 44. The source and drain electrodes 42 and 44 are spaced apart from each other and overlap opposite ends of the gate electrode 32. The data line 40 is also formed with the source and drain electrodes 42 and 44. Thereafter, a portion of the ohmic contact layer 38 disposed upon the active layer 37 is etched using the source and drain electrodes 42 and 44 as masks, thereby forming first and second ohmic contact layers 38a and 38b and a channel region-between the source electrode 42 and the drain electrode 44. Therefore, the inverted staggered type TFT “S” of FIG. 3, which includes the gate electrode 32, the active layer 37, the first and second ohmic contact layers 38a and 38b, and the source and drain electrodes 42 and 44, is complete. Further, the second connecting line 34 of FIG. 3 can be formed with the source and drain electrodes 42 and 44.
Still referring to FIG. 4C, a portion of the gate insulation layer on the first connecting line 31 is removed to expose a portion of the first connecting line 31. Thereafter, the exposed portion of the first connecting line 31 is eliminated in order to electrically cut the first connecting line 31.
In FIG. 4D, a passivation layer 45 is formed on and over an entire surface of the transparent substrate 1 in order to cover the inverted staggered type TFT and gate insulation layer 34. The passivation layer 45 is silicon nitride (SiNX), silicon oxide (SiOX) or benzocyclobutene (BCB). Then, a photo resist 47 is formed on the passivation layer 45 using a spin coat method, and then exposed to light using a mask. Thereafter, the photo resist 47 is developed to form an etching hole 48 over the drain electrode 44.
After forming the etching hole 48, the array substrate is put into an etching chamber in order to form a drain contact hole 49 of FIG. 4E. Namely, a portion of the passivation layer 45 over the drain electrode 44, as shown in FIG. 4E, is removed to form the drain contact hole 49. Thereafter, the photo resist formed on the passivation layer 45 is completely eliminated. Referring to FIG. 4E, a transparent conductive material including at least indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited and patterned to form pixel electrode 14 that connects with the drain electrode 44 through the drain contact hole 49.
The conventional array substrate for use in the LCD device is commonly fabricated by the above-mentioned processes. However, in a large LCD device that needs to have high resolution, a signal delay may occur on the gate lines due to electrical resistance of the gate lines. Therefore, cross talk may occur between the gate lines and the pixel electrodes, thereby deteriorating image quality.
In order to overcome this problem, aluminum (Al) is conventionally used as a metal for the first metal layer because of its low resistance and reduced signal delay. However, pure aluminum is chemically weak when exposed to acidic processing and may result in formation of hillocks during high temperature processing. Accordingly, multi-layered aluminum structures are used for the first metal layer. Namely, the aluminum (Al) layer is stacked with a molybdenum (Mo) layer that has high corrosion resistance and durability.
When the molybdenum (Mo) layer is formed on the first metal layer (i.e., the aluminum layer) in the above-mentioned formation of the array substrate, a deposition process that forms the Mo layer on the Al layer is required. In addition, etching the Mo layer and etching the Al layer are also necessary, respectively. In these etching processes, a different etchant is needed for each metal layer. Thus, this double-layered structure decreases manufacturing yield and increases a chance to deteriorate the array substrate, thereby raising an occurrence of defects.
The double-layered structure in the array substrate will be explained in accordance with FIGS. 5, 6A-6E, and 7A-7E. Here, the array substrate has coplanar type TFTs as switching devices.
Amorphous silicon (a-Si) is widely used as an active layer of the TFT in an array substrate for use in liquid crystal display (LCD) devices. That is because amorphous silicon is possibly formed on the low cost glass substrate at a low temperature to form the large LCD panel. However, the TFT including polycrystalline silicon (poly-Si) for use in the liquid crystal display device has been researched and developed. It is easy to obtain fast response time in display when using the polycrystalline silicon as an element of the TFT in the liquid crystal display device rather than when using the amorphous silicon as an element of the TFT. Namely, field effect mobility in poly-Si is 100 to 200 times faster than that in a-Si. Additionally, the poly-Si has a good stability against light and temperature variation.
Now, the coplanar type TFT having poly-Si as an active layer will be explained. FIG. 5 is a schematic partial plan view of an array substrate having coplanar type TFTs, FIGS. 6A to 6E are cross-sectional views taken along the line VI—VI of FIG. 5, and FIGS. 7A to 7E are cross-sectional views taken along the line VII—VII of FIG. 5.
Referring to FIG. 5, gate lines 51 are arranged transversely and data lines 71 are arranged in a longitudinal direction perpendicular to the gate lines 51. The gate lines 51 and data lines 71 define pixel regions, and each pixel electrode 91 is positioned in each pixel region. Although as shown in FIG. 5 the pixel electrodes 91 overlap the gate lines 51 and data lines 71, it is not required that the gate lines 51 overlap the data lines 71. At one corner of each pixel region, a coplanar type TFT “T” is positioned near the crossover point of each gate line 51 and data line 71. At the ends of the gate lines 51, a gate driving circuit “G” is electrically connected to all gate lines 51. Further, all of the data lines 71 are also electrically connected to a data driving circuit (not shown) at the ends of the data lines 71. A gate shorting bar 54 is disposed parallel with the data lines 71 at the peripheral portion of the substrate. Also, a data shorting bar (not shown) is disposed parallel with the gate lines 51 at the other adjacent peripheral portion of the substrate.
In the coplanar type TFT “T” of FIG. 5, a gate electrode 53 extending from the gate line 51 is disposed over an active layer 50 including polycrystalline silicon. A source electrode 72a extending from the data line 71 contacts the active layer 50 through a first contact hole 61, and a drain electrode 72b positioned opposite to the source electrode 72a contacts the active layer 50 through a second contact hole 62. Further, a portion of the pixel electrode 91 contacts the drain electrode 72b through a third contact hole 81.
The fabrication processes will be explained in accordance with FIGS. 6A-6E and 7A-7E. FIGS. 6A to 6E show the fabrication process steps of the TFT “T” of FIG. 5, and FIGS. 7A to 7E show the fabrication process steps of the shorting bar 54 of FIG. 5, respectively corresponding to FIGS. 6A to 6E.
Referring to FIGS. 6A and 7A, a buffer layer 24 is formed on a transparent substrate 10, and then the active layer 50 (i.e., polycrystalline silicon) having an island shape is formed on the buffer layer 24. Therefore, the buffer layer 24 and the active layer 50 are stacked in an area for the TFT, while only the buffer layer 24 is stacked in an area for the shorting bar of FIG. 5.
In FIGS. 6B and 7B, a gate insulation layer 26 that is made from silicon nitride or silicon oxide is formed on an entire surface of the buffer layer 24 to cover the active, layer 50. Thereafter, a first metal layer 52a and a second metal layer 52b are formed in series on the gate insulation layer 26. The first metal layer 52a is usually a metallic material having a low resistance, such as pure aluminum or aluminum alloy (for example, aluminum neodymium (AlNd)). The second metal layer 52b is usually a metallic material having high corrosion resistance and durability, such as molybdenum. Thus, the second metal layer 52b protects the first metal layer 52a and prevents the formation of hillocks. Then, the first and second metal layers 52a and 52b are patterned together in order to form the gate electrode 53 over the active layer 50, the shorting bar 54 in a periphery of the substrate, and the gate lines 51 of FIG. 5. All the elements made of the first and second metal layers 52a and 52b have the double-layered structure as shown in FIGS. 6B and 7B.
Still referring to FIGS. 6B and 7B, after patterning the first and second layers 52a and 52b, an ion doping process is performed to the active layer 50 using the gate electrode 53 as a mask. Namely, the active layer 50 is introduced by n+(or p+) ion doping (plasma doping) using the gate electrode 53 as a mask, and thus a source contact area 50a and a drain contact area 50b are formed at both sides of the active layer 50. At this time, the gate electrode 53 acts as an ion-stopper that prevents the dopant (n+ or p+ ion) from penetrating into a portion of polycrystalline silicon (the active layer 50) under the gate electrode 53. Therefore, the portion of active layer 50 under the gate electrode 53 remains as a pure silicon area, while the source and drain contact areas 50a and 50b doped by the dopant become impure silicon areas.
Now, referring to FIGS. 6C and 7C, an interlayer insulator 60, which is made of silicon nitride or silicon oxide, is formed on the gate insulation layer 26 to cover the patterned first and second metal layer 52a and 52b. Thereafter, the first contact hole 61 to the source contact area 50a and the second contact hole 62 to the drain contact area 50b are formed by patterning both the interlayer insulator 60 and the gate insulation layer 26. An etching hole 64 to the shorting bar 54 is formed at this time with the contact holes 61 and 62.
In FIGS. 6D and 7D, a third metal layer, such as molybdenum, is formed on the above-mentioned intermediates, and then patterned to form the source electrode 72a and drain electrode 72b. Thus, the coplanar type TFT “T” of FIG. 5 is complete. Additionally, the data lines 71 of FIG. 5 are formed at the time when forming the source and drain electrodes 72a and 72b. As mentioned before, each data line 71 is substantially perpendicular to the gate lines 51 of FIG. 5. The source electrode 72a, as shown in FIG. 6D, contacts the source contact area 50a of active layer 50 through the first contact hole 61, while the drain electrode 72b contacts the drain contact area 50b of active layer 50 through the second contact hole 62.
Referring to FIG. 7D, although the third metal layer is formed on the shorting bar 54 and into the etching hole 64, this third metal layer is eliminated when forming the source and drain electrodes 72a and 72b. Moreover, a portion of the shorting bar 54 under the etching hole 64 is also removed during this patterning process. In other words, a portion of the double-layered shorting bar 54 (first and second metal layers) is removed during the etching process that forms the source and drain electrodes 72a and 72b to electrically disconnect the shorting bar 54. The reason for cutting the double-layered shorting bar 54 is to electrically isolate each gate line 51 of FIG. 5. Further, since the gate driving circuit “G” of FIG. 5 is electrically connected to the gate lines 51, the gate shorting bar 54 preventing the discharge of the static electricity is not required anymore.
Thereafter, a passivation layer 66 made of silicon nitride is formed on the interlayer insulator 60 filling the etching hole 64 and on the coplanar type TFT covering the source and drain electrodes 72a and 72b. 
Now, referring to FIGS. 6E and 7E, a planar layer 80 that is formed of benzocyclobutene (BCB) is formed on an entire surface of the passivation layer 66 in order to planarize the array substrate. After that, portions of the planar layer 80 and passivation layer 66 over the drain electrode 72b are patterned to form the third contact hole 81 exposing a portion of the drain electrode 72b. Then, a transparent conductive material is formed on the planar layer 80 having the third contact hole 81, and then patterned to form the pixel electrode 91 in the pixel region. As a result, the pixel electrode 91 electrically contacts the drain electrode 72b through the third contact hole 81.
As aforementioned, the gate shorting bar is electrically cut when the source and drain electrodes are formed by patterning the third metal layer. When patterning the third metal layer, a wet-etching method is commonly used. However, since the gate shorting bar has a double-layered structure (first metal layer, e.g., aluminum, and second metal layer, e.g., molybdenum), an additional wet-etching process is required to electrically cut the gate shorting bar. In other words, since the second metal layer of the gate shorting bar is made of the same material as the third metal layer, it is etched when forming the source and gate electrodes. However, since the first metal layer is different from the second and third metal layers, the additional wet-etching process and etchant are necessary.
As a result, the substrate is introduced to the two different etchants, thereby causing defects in the substrate. Further, if the etching process time is reduced in order to prevent the defects, the gate shorting bar is not disconnected electrically, and thus proper operation of the LCD device can not be obtained.